1. Technical Field
The present invention generally relates to flash memory devices, and more particularly, to a method of forming selection transistors as memory transistors in a NAND type flash EEPROM.
2. Discussion of the Related Art
Non-volatile memory devices, such as flash memory devices, may be provided in a NOR-type configuration or a NAND-type configuration and can be electrically rewritten and formed with high integration density. NAND-type nonvolatile semiconductor memory devices include a plurality of NAND cell units. Each NAND cell unit is configured by serially connecting a plurality of memory transistors in a column direction between a source and a drain. Selection gate (SG) transistors are connected to at each end of the series-connected memory transistor circuit.
Two types of non-volatile memory transistors are floating gate type memory transistors and floating trap (charge trap) type memory transistors. A floating gate type memory transistor includes a control gate and a conductive floating gate that is isolated, by an insulating layer, from a field effect transistor (FET) channel formed in a substrate. Floating gate type memory transistors may be programmed by storing charges as free carriers on the conductive floating gate.
A floating gate type memory transistor is similar to a standard MOSFET transistor, except that it has two gates instead of just one. One gate is the control gate (CG) like in other MOSFET transistors, but the second gate is a floating gate (FG) that is insulated all around by an oxide insulator. Because the FG is isolated by its insulating oxide layer, any electrons placed on it get trapped there and thus store the information.
When electrons are trapped on the FG, they modify (partially cancel out) an electric field coming from the CG, which modifies the threshold voltage (Vt) of the cell. Thus, when the cell is “read” by placing a specific voltage on the control gate (CG), electrical current will either flow or not flow between the cell's source and drain connections, depending on the threshold voltage (Vt) of the cell. This presence or absence of current is sensed and translated into 1's and 0's, reproducing the stored data.
Floating trap (charge trap) type memory transistors may include a non-conductive charge storage layer between a gate electrode and a field effect transistor (FET) channel formed in a substrate. Floating trap type memory transistors may be programmed by storing charges in traps in the non-conductive charge storage layer.
When a positive voltage is applied on the gate electrode, electrons are tunneled via the tunneling insulating layer to become trapped in the charge storage layer. As the electrons are accumulated in the charge storage layer, a threshold voltage of the memory transistor is increased, and the memory transistor becomes programmed. In contrast, when a negative voltage is applied to the gate electrode, trapped electrons are discharged to the semiconductor substrate via the tunneling insulating layer. Concurrently, holes become trapped by the tunneling insulating layer. Consequently, the threshold voltage of the memory transistor is decreased, and the memory transistor becomes erased.
Conventional NAND Flash memory strings typically are isolated from other strings by shallow trench isolation (STI), that prevents electrical current leakage between adjacent semiconductor device components, and have three types of transistors which are: the memory transistor transistors (implementing nonvolatile data-storage memory transistors); string select transistors SST; and ground select transistors GST. Typically, in a NAND flash memory device, string selection and ground selection transistors (SSL and GSL) are disposed at the ends of a NAND string and are used to select the NAND string during program, erase and read operations.
A group of NAND cell units (NAND strings) arranged in a row direction is called a NAND cell block (memory block, MB). The gates of selection transistors SST and GST arranged on the same row are commonly connected to a corresponding one of selection gate lines and the control gates of memory transistors arranged on the same row are commonly connected to a corresponding one of control gate lines. If n memory transistors are serially connected in the NAND cell unit, the number of control gate lines of memory transistors contained in one NAND cell block is n.
When programming data, first, all data items stored in all memory transistors of memory storage cells in the entire memory block (MB) are simultaneously erased. The erase process is performed by setting all of the control gate lines (word lines) of memory transistors in the selected memory block to a low voltage Vss (for example, 0V) and applying high positive voltage Vera (erase voltage, for example, 20V) to a p-type well region in which the memory cell array is formed to discharge electrons in the floating gates into the channel regions. As a result, all data items stored in all memory transistors of memory storage cells in the entire memory block are all set to “1” data. Multiple or all memory blocks can be simultaneously erased.
After the above-described simultaneous data erase step, the data programming process is simultaneously performed for a plurality of memory transistors connected to a selected control gate line. The unit of binary data to be programmed in the memory transistors connected to a selected control gate line is generally defined as one “page” of data. The “page” order in which data is programmed into the memory transistors (pages) in the memory block is based either on a system in which data is programmed in a random order (random programming process) or on a system in which data is sequentially programmed in one direction (sequential programming process). In the sequential programming process, generally, data is programmed in sequential pages in order from the source-side memory transistor.
If high positive voltage Vpgm (program voltage, for example, 20V) is applied to a selected control gate line in the simultaneous programming process, electrons are injected from the channel of the memory transistor into the floating gate in the case of “0” data (so-called “0” programming or “0” write). In this case, injection of electrons is inhibited in the case of “1” data (so-called program inhibition, “1” programming or “1” write). Thus, while writing random data into memory transistors of one page, two types of data programming operations are simultaneously performed and it is necessary to control the channel voltage of each memory transistor according to its program data. For example, in the case of “0” data, the channel voltage is kept low so as to apply a strong electric field to the gate insulating film under the floating gate when the program voltage Vpgm is applied to the control gate. In the case of “1” data, the channel voltage is boosted so as to make weak the electric field applied to the gate insulating film and inhibit injection of electrons into the floating gate. If the channel voltage is insufficiently boosted, electrons are injected so that the threshold voltage of the memory transistor to be subjected to the “1” programming process will be changed. This phenomenon is referred as “erroneous programming” or “write error” or “program disturb”. Therefore, in order to realize the programming operation of the NAND type flash EEPROM, it is necessary to suppress variation in the threshold voltage due to erroneous programming within a specified range so as not to cause erroneous operation.
In a conventional NAND Flash memory string, the select transistors SST and GST are standard MOSFET transistors, each having one control gate.
A leakage current may occur in unselected strings in unselected blocks during a read operation of a selected block, thereby causing read error to occur. Hence, it is necessary to control the leakage current of the select transistor. To this end, conventionally a threshold voltage implant is performed during manufacture in the select transistor region, requiring additional (e.g., mask, implantation) steps in a method of manufacturing the NAND flash memory device.
For the purpose of controlling threshold-voltage distributions of programmed memory cells densely and precisely, an incremental step pulse programming (ISPP) mode is often used. According to the ISPP mode, a programming voltage applied to a word line rises stepwise up during repetition of loops of programming cycle. The programming voltage increases by a predetermined step increment (ΔV), also referred to as a “rising rate”. During the programming sequence, a cell threshold voltage of a programmed cell increases at a rate predetermined for each programming loop. Programming of a nonvolatile memory device by means of the ISPP mode is disclosed in U.S. Pat. No. 6,266,270, entitled “Non-Volatile Semiconductor Memory and Programming Method of the Same”. Each programming loop generally is divided into programming and program-verifying periods. In the programming period, memory cells are programmed under a given bias condition as is well known in this art. In the program-verifying period, the memory cells programmed once are verified whether they are conditioned in the target threshold voltages. The programming loops are repeated for a predetermined number of times until all memory cells are completely programmed at the target threshold voltages. As well known, the program-verifying operation is similar to a reading operation, except that read data is not output to external of the device.